1. Field of the Invention
The present invention relates to a differential amplifier, a reference voltage generating circuit in which the differential amplifier is used, a differential amplifying method, and a reference voltage generating method in which the differential amplifying method is adopted. Particularly the invention relates to a differential amplifier provided with a circuit that reduces an input offset, a reference voltage generating circuit in which the differential amplifier is used, a differential amplifying method in which the input offset is reduced, and a reference voltage generating method in which the differential amplifying method is adopted.
2. Description of the Related Art
Recently a power supply voltage used in an analog circuit tends to be lowered in order to achieve reduction of power consumption and speed enhancement. For example, Japanese Patent Application Laid-Open (JP-A) Nos. 2006-023920 (corresponding to U.S. Pat. No. 7,215,183), 2007-300623 (corresponding to U.S. Pat. No. 7,336,138), and H05-075431 disclose techniques regarding the differential amplifier applied to the analog circuit. A technique regarding the reference voltage generating circuit in which the differential amplifier is used is disclosed in H. Banba et al, “A CMOS Bandgap Reference Circuit with Sub-1-V Operation” in IEEE Journal of Solid-State Circuits, Vol. 34, No. 5, May 1999, p. 670-673 (hereinafter referred to as Non-Patent Document 1).
The entire disclosures of the aforementioned patent and Non-patent documents are incorporated herein by reference thereto.
However, in the reference voltage generating circuit disclosed in Non-Patent Document 1, the inventor shows that accuracy of output reference voltage is lowered with decreasing power supply voltage and a characteristic of the differential amplifier used has an influence on the lowering of the accuracy. FIG. 9 is a circuit diagram produced by the inventor based on the reference voltage generating circuit disclosed in Non-Patent Document 1, and FIG. 9 is an explanatory view illustrating the problem of the lowering of the accuracy of the reference voltage. In cases where the reference voltage generating circuit (reference voltage generating circuit in which a bandgap circuit is used) of FIG. 9 is operated at a low voltage, dependence of reference voltage output Vref on a power supply voltage is increased as the power supply voltage is lowered. When the dependence on the power supply voltage is increased, the reference voltage is largely changed by the slight change in power supply voltage, and therefore the reference voltage becomes unstable. This means the accuracy of the reference voltage comes down. A factor the dependence of the reference voltage output Vref on the power supply voltage is increased includes an insufficient output resistance of constant current source MOS (Metal Oxide Semiconductor) in an output stage and an input offset voltage generated by a finite gain of a differential amplifier used in the circuit, and the latter is the main factor. The input offset voltage of the differential amplifier, which becomes the main factor in lowering the accuracy of reference voltage supplied from the reference voltage generating circuit, will be described with reference to FIG. 18. The differential amplifier of FIG. 18 includes a differential pair of NMOS (N-type MOS) transistors and current mirror type load circuit of PMOS (P-type MOS) transistors, and an output is brought into contact with a negative input terminal to form a voltage follower circuit. When the differential amplifier has a sufficiently high amplification factor, potentials at a positive input terminal and an output terminal are equal to each other in the differential amplifier. However, because the differential amplifier has the finite amplification factor, a slight potential difference remains between the positive input voltage and the output voltage. This is the input offset voltage. The input offset will be described in detail. In the differential amplifier of FIG. 18, it is assumed that gm is mutual conductance of the differential pair of NMOS transistors and rds is a drain resistance of the current mirror type load circuit of the PMOS transistors that become a load. It is also assumed that VOUTb is a potential at gates commonly connected in the current mirror type load circuit of the PMOS transistors and VOUT is a potential at the outputs of the PMOS transistors. At this point, (VDD-VOUTb) is a drain-source voltage of the diode-connected PMOS transistor while (VDD-VOUT) is a drain-source voltage of the PMOS transistor connected to the output side. Accordingly, a drain voltage difference ΔVDSp between the PMOS transistors is expressed by an equation (1):ΔVDSp=(VDD−VOUTb)−(VDD−VOUT)=VOUT−VOUTb  (1)
A current error ΔIp caused by the drain voltage difference ΔVDSp in the current mirror type load circuit is expressed by an equation (2):ΔIp=ΔVDSp/rds=(VOUT−VOUTb)/rsd  (2)
On the other hand, an input offset voltage ΔVIN is expressed by an equation (3):ΔVIN=VIN−VOUT  (3)
A current difference ΔIn caused by the input offset voltage ΔVIN in the differential pair of NMOS transistors is expressed by an equation (4):ΔIn=gm·ΔVIN=gm·(VIN−VOUT)  (4)
Because ΔIp and ΔIn are equal to each other, the input offset voltage ΔVIN can be expressed as follows from the equations (2) and (4):ΔVIN=(VOUT−VOUTb)/(gm·rsd)  (5)
As can be seen from the equation (5), there are two methods of reducing the input offset voltage ΔVIN.
(1) A voltage amplification factor Av=gm·rds of the differential amplifier circuit is increased.
(2) The potential VOUTb at the gates commonly connected in the current mirror type load circuit of the PMOS transistors is equalized to the potential VOUT at the outputs of the PMOS transistors (VOUT=VOUTb).
As to the first method, the drain resistance rds is increased by forming the current mirror type load circuit into a cascode type load circuit, thereby increasing the voltage amplification factor Av=gm·rds of the differential amplifier circuit. However, disadvantageously an operating range of the power supply voltage is degraded by a voltage necessary for the cascode type load circuit. Therefore, particularly the first method is not suitable to a low-power circuit. As to the second method, the potential VOUTb at the gates commonly connected in the current mirror type load circuit of the PMOS transistors is substantially determined by threshold voltages of the PMOS transistors. On the other hand, the potential VOUT at the output of the current mirror type load circuit of the PMOS transistors is determined by a circuit configuration, and generally the potential VOUTb and the potential VOUT are hardly equalized to each other in any state. Although JP-A Nos. 2006-023920, 2007-300623, and H05-075431 disclose the reference voltage generating circuit operated at a low voltage, there is no suggestion about the influence of the input offset voltage on the accuracy of output voltage. Accordingly, even if the disclosed techniques are referred to, unfortunately there is no suggestion about the differential amplifier that can be used at a low voltage without the influence of the input offset voltage and the reference voltage generating circuit.